Binary Vector-Vector Multiplier with BIST
Field
IC design
Institution
RIT
Year
2023
Project Type
Individual
Course
Digital IC Design
Keywords
IC Design, Cadence, BIST, Vector-vector Multiplier, Layout, Golden signature, Parasitic Delay
This project aims to design a circuit that can perform binary vector-vector multipliers including BIST. Some of the key component required includes, but not limited to: a vectorvector multiplier circuit, storage capability, and built-in self-test module. Some of the key processes include, but not limited to: building a circuit that performs the required function, finding a golden signature, building a layout based on the circuit, and testing and analysis on results and delay.
Introduction
This capstone project represents the culmination of a course focused on advanced circuit design, where I applied knowledge of schematic-based layouts, delay and power consumption calculations, and parasitic delay testing. Tasked with designing a binary vector-vector multiplier circuit equipped with a Built-In Self-Test (BIST) module, the project aimed to enhance the efficiency of AI-driven devices by serving as a hardware accelerator. The circuit operates with two input vectors, 'u' containing binary values and 'w' with ternary values, outputting a single bit based on their dot product. Featuring dual modes for standard operation and self-testing, the circuit generates pseudo-random vectors for reliability verification against a golden signature. The gate layouts were crafted during lab sessions, culminating in a fully tested circuit design.
[The high level design flow chart can be seen on the right]
partial dot product logic
adder matrix for compiling the ‘Y’ outputs
binary transformation
Design Methodology
The design methodology for this binary vector-vector multiplier project with a BIST module is grounded in a balance between conceptual understanding and practical application.This methodology highlights a practical approach to complex circuit design, prioritizing functionality and testing accuracy while addressing the challenges of timing and layout integration.
-
The project begins with an abstract schematic, illustrating basic design elements such as input vectors, clock signals, and control lines.
-
A hybrid input approach is adopted, using parallel inputs for the 'u' vector due to its simpler structure and serial inputs for the 'w' vector to minimize circuit complexity and size.
-
For testing, a 6-bit pseudo-random sequence generator (PRSG) creates a golden signature, ensuring circuit reliability.
-
The multiplication logic uses Boolean equations and K-mapping techniques to handle the dot product of 1's complement encoded 'w' vector and binary 'u' vector.
-
An adder matrix compiles the multiplication outputs, and a 2's complement conversion facilitates binary subtraction to determine the final dot product result.
-
Special logic is implemented to differentiate between '0' and negative results.
-
Design decisions shifted from optimizing for area to focusing on performance, due to time constraints and troubleshooting needs.
-
Gated clock signals are employed to manage timing for the hybrid input design, ensuring accurate BIST functionality.
-
The layout strategy involves building sub-circuits individually before integrating them into the master layout, with a trade-off between area efficiency and completion time.
Preliminary Testing
Preliminary testing is a critical step in validating the functionality of complex circuit designs. These tests not only ensured that each part of the circuit worked independently but also verified their correct integration, paving the way for a fully functional end design.
-
Initial tests revealed that the circuit did not function as expected on the first attempt, indicating possible issues at a lower-level circuit.
-
Focused testing on the 4-bit adders, composed of mirrored adders and XOR gates, was conducted to ensure the reliability of all subsequent adders in the circuit.
-
A specific test setup illustrated in the figures involved setting certain inputs to '1' and performing binary addition to validate the adder's logic.
-
Successful output from the 4-bit adder test showed correct voltage levels, confirming the functionality of this component.
-
Comprehensive testing on other components like the dot product, adder matrix, and the final 'Yout' computation circuit followed similar logic but is not detailed in the report to avoid redundancy.
-
The root cause of the initial malfunction was traced back to the select line control logic, leading to the implementation of gated clock signals for better control over different circuit sections.
Stimuli setup for 4-bit adder test
waveform output for 4-bit adder test
the output waveform of the golden signature
delay measurement
Analysis
The analysis phase of the circuit project was instrumental in verifying the circuit's functionality through a series of methodical tests. These tests were crucial in fine-tuning the circuit's performance and ensuring its reliability, underscoring the importance of detailed analysis in circuit design and validation.
-
The goal was to ensure the scan chain's output matched the golden signature, confirming the circuit's operation.
-
A testbench cell view was created for generating inputs and controlling timing, interfacing directly with the master schematic.
-
Behavior for the testbench was defined using a Verilog file, structured as per the lab's tutorial, which initializes all inputs to zero and then sequentially inputs the 'w' weights and 'u' vector values.
-
The testbench setup allowed the BIST to receive inputs and generate an output to be compared with the expected golden signature.
-
The testing process revealed issues that, once resolved, produced an output matching the golden signature, verifying the circuit's accuracy.
-
The waveforms captured during testing confirmed the correct timing and behavior of the Verilog file, with the clock stopping after the necessary cycles to observe the golden signature.
-
The propagation delay was successfully measured at approximately 810.5233 picoseconds.
In conclusion, this project adeptly melded foundational concepts from coursework with advanced challenges in circuit design and problem-solving. Utilizing tools like Cadence for layout design and incorporating methods such as K-mapping and complementary arithmetic, the vector-to-vector multiplier circuit was effectively realized. While the BIST component introduced complexity, it was successfully navigated to understand and implement PRSG and SISR techniques. Overall, the project reinforced critical IC design skills and offered valuable hands-on experience with design freedom, serving as both a practical application of classroom learning and a stepping stone for future innovation in integrated circuit design.